embedded - Error (10170): Verilog HDL syntax error at final_lab.sv(46) near text "default"; expecting "end" -

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hello getting following error in verilog , don't know why can't seem figure out. please

error : error (10170): verilog hdl syntax error @ final_lab.sv(46) near text "default"; expecting "end"

code 

module final_lab (clock_50,  sw, ledr, key, hex5, hex4, hex3, hex2, hex1,hex0);      input logic clock_50;      input logic [6:1] sw;      input logic [3:0] key;      output logic [9:0] ledr;      output logic [6:0] hex5, hex4, hex3, hex2, hex1, hex0;      logic [6:1] whatwehave;     logic reset;     logic keyone , keythree;         assign whatwehave = 6'b000000;      always_comb          begin         if (whatwehave[6:1] == sw[6:1])             begin             keythree = 0;             keyone = 0;             whatwehave = whatwehave;             end          else if (whatwehave[6:1] < sw[6:1])             begin             whatwehave = whatwehave+1;             keythree = 1;             keyone = 0;             end          else if (whatwehave[6:1] > sw[6:1])             begin             whatwehave = whatwehave-1;             keyone = 1;             keythree = 0;             end          else             begin             whatwehave = whatwehave;             keyone = 0;             keythree = 0;              end           default             begin              whatwehave = 6'bxxxxxx;             keyone = 1'bx;             keythree = 1'bx;             end         end       normallight 1 (.clk(clock_50), .reset(sw[9]), .l(keythree), .r(keyzero), .nl(ledr[2]), .nr(1'b0), .lighton(ledr[1]));      normallight 2 (.clk(clock_50), .reset(sw[9]), .l(keythree), .r(keyzero), .nl(ledr[3]), .nr(ledr[1]), .lighton(ledr[2]));      normallight 3 (.clk(clock_50), .reset(sw[9]), .l(keythree), .r(keyzero), .nl(ledr[4]), .nr(ledr[2]), .lighton(ledr[3]));      normallight 4 (.clk(clock_50), .reset(sw[9]), .l(keythree), .r(keyzero), .nl(ledr[5]), .nr(ledr[3]), .lighton(ledr[4]));      normallightlight 5 (.clk(clock_50), .reset(sw[9]), .l(keythree), .r(keyzero), .nl(ledr[6]), .nr(ledr[4]), .lighton(ledr[5]));      normallight 6 (.clk(clock_50), .reset(sw[9]), .l(keythree), .r(keyzero), .nl(1'b0), .nr(ledr[5]), .lighton(ledr[6])); endmodule

the place default used in logic inappropriate. default keyword used along case statements , not if-else conditions.

in nested if-else, final else (without condition) executed similar default. looks trying have 2 default conditions. try rework logic.


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