c - How bits of this register is set in u-boot -

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i trying figure out how "sram_ctl1_cfg" register's 4th , 5th bit set using following statement in u-boot:

/* map sram emac */    setbits_le32(&sram->ctrl1, 0x5 << 2);

http://git.denx.de/?p=u-boot.git;a=blob;f=drivers/net/sunxi_emac.c;h=11cd0ea06888ba8e271b0c10376306df5291a3e2;hb=head#l503

as per datasheet if bit 4:5 of "sram_ctl1_cfg" become "01" sram mapped emac peripheral.

http://linux-sunxi.org/sram_controller_register_guide

shouldn't setbits_le32(&sram->ctrl1, 0x5 << 2) setbits_le32(&sram->ctrl1, 0x4 << 2)?

so, answer yes, (0x5 << 2), 20 decimal 010100 in binary , set '4:5' '01' emac setting bit 2 1. setting bit 2 1 magic value we're setting because it's being set (presumably, didn't trace of history back) in sources allwinner provides, without further explanation. setting (0x4 << 2) set claimed registers have hidden breakage on other boards magic value required too.


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