math - instancing modules verilog -

i have created 2 verilog modules instance in third module. inputs of third module feed first, , outputs of first inputs of second module , outputs of second module outputs of overall module, if show example of how in generic manner appreciated. art

it's easy this:

module 1 (input i, output o);   assign o = i; endmodule  module 2 (input i, output o);   assign o = i; endmodule  module top (input i, output o);    wire w;    1 inst1 (.i(i), .o(w));   2 inst2 (.i(w), .o(o));  endmodule 

http://www.edaplayground.com/x/2mca

by default, inputs , outputs wires. can connect them straight module inputs , outputs. need 1 or more internal wires internal connection(s).