fpga - How to use Quartus to optimize combinational logic? -

i using quartus synthesize combinational circuit fpga. right want best possible maximum frequency without considering resource consumption. current critical path composed sequence of multiplications this:

res = * b * c *d 

i wondering whether possible quartus automatically generate equivalent combinational logic has shorter critical path this:

ab  = * b cd  = c * d res = ab * cd 

which have 2 multipliers on critical path. found online document quartus mentioned possible without instructions on how it:usingtimequestanalyzer

pipelining doesn't work here since don't want change timing of combinational circuitry.

a synthesis tool quartus builds initial internal structure based on hdl (vhdl/verilog) code, , reorganize , optimizes structure depending on constrains , area, extend tool has rules manipulating structures. tool timing check see timing adhered resulting design.

for implementation of multiplication * operator, appears quartus implements a * b * c * d using left associative property of *, ((a * b) * c) * d, , not apply associative rule make (a * b) * (c * d) in order meet timing requirements.

so if want make multiplier like:

res = (a * b) * (c * d) 

you can synthesis tool writing hdl (vhdl used):

ab <= * b; cd <= c * d; res <= ab * cd; 

and remember make timing constrains matches requirements, check resulting implementation meets required timing. path requirements can made like, a res maximum of 12 ns delay:

set_max_delay -from [get_ports a[*]] -to [get_ports res[*]] 12 ... 

the rtl , technology structure in figure:

where expression res = * b * c * d gives structure:

and timing follows implementation expected.

so can control implementation through structure of hdl code, if structure advise hdl code meet timing, , synthesis tool can't optimize further area while still meeting timing requirements.